Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration

Xiaoyun Li; Houpeng Chen; Qian Wang; Xi Li; Yu Lei; Qi Zhang; Xi Fan; Jiajun Hu; Zhen Tian; Zhitang Song

doi:10.1587/elex.14.20160901

LETTER

Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration

Xiaoyun Li, Houpeng Chen, Qian Wang, Xi Li, Yu Lei, Qi Zhang, Xi Fan, Jiajun Hu, Zhen Tian, Zhitang Song

Author information

Xiaoyun Li
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Houpeng Chen
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Qian Wang
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Xi Li
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Yu Lei
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Qi Zhang
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Xi Fan
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Jiajun Hu
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Zhen Tian
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences
Zhitang Song
State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences

Keywords: electrostatic discharge (ESD), power clamp, mixed-voltage I/O, high discharge current, SOI CMOS process, 28 nm high-k CMOS process

JOURNAL FREE ACCESS

2017 Volume 14 Issue 2 Pages 20160901

DOI https://doi.org/10.1587/elex.14.20160901

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Abstract

An enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration was presented. Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18 µm silicon-on-insulator (SOI) CMOS process and 28 nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.

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