A PMOS read-port 8T SRAM cell with optimized leakage power and enhanced performance

抄録

This paper presents a novel PMOS read-port 8T SRAM cell, in which the read circuit is constructed by two cascaded PMOS transistors, and hence the leakage power is significantly optimized compared to the conventional 8T cell. Meanwhile, it also exhibits high area efficiency due to an equalized quantity of NMOS and PMOS transistors per cell. Furthermore, the proposed cell has sufficient potential to enhance performance by employing a Half-Schmitt inverter. The measurements indicate that the proposed cell outmatches conventional 8T cell in terms of leakage suppression and area saving, thus making it a superior choice for ultra low power applications.