Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

Abstract

In this study, the common gate stage of the conventional inductive degeneration cascode LNA operating in 60GHz V-band for the upcoming Wi-Fi standard, and 802.11ad standard with data rates up to 7Gbit/sec was linearized by bilateral CMOS resistor. The proposed method linearizes the LNA by 6dBm with minimum power consumption. The proposed LNA dissipates only 2.05mW supplied from 1.8V voltage source and exhibits a minimum noise figure of 6.8dB in the operating frequency. The LNA, without the proposed linearization technique, exhibited 7dB gain. The linearized LNA exhibited 3.5dB gain.

The ADS2016.01 with TSMC 180nm CMOS model files were used to perform the simulation.