Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

Abstract

In this study, the common gate stage of the conventional inductive degeneration cascode LNA operating in 60 GHz V-band for the upcoming Wi-Fi standard, and 802.11ad standard with data rates up to 7 Gbit/sec was linearized by bilateral CMOS resistor. The proposed method linearizes the LNA by 6 dBm with minimum power consumption. The proposed LNA dissipates only 2.05 mW supplied from 1.8 V voltage source and exhibits a minimum noise figure of 6.8 dB in the operating frequency. The LNA, without the proposed linearization technique, exhibited 7 dB gain. The linearized LNA exhibited 3.5 dB gain.

The ADS2016.01 with TSMC 180 nm CMOS model files were used to perform the simulation.