Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS

抄録

New generation space-borne SAR (synthetic aperture radar) systems require high real-time processing performance and have size, weight and power constrains. This paper presents a multi-channel stripmap SAR imaging system implemented on an FPGA platform. In order to reduce FPGA design cost, a high-level synthesis tool Xilinx Vivado HLS is applied to design and implement the SAR imaging system. FFT algorithms in the imaging algorithm use FFT IP cores in FPGA, and the rest is customized on HLS. The modules designed on HLS are optimized and packaged as IP blocks for FPGA implementation of the imaging system. The performance and resource utilization of the whole system are evaluated by processing a two-channel SAR raw data with a granularity of 16384×4096. The system can complete imaging in about 4.7 s at 100MHz operating frequency.