A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

抄録

This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-of-Merit (FoM) of the total SAR ADC chip. The measurement results show the ADC achieves an SNDR of 35.5 dB at the input frequency of 318.8 MHz. The chip consumes 4.0 mW including the SAR ADC core and the reference voltage buffer, resulting in an FoM of 117.8 fJ/conv.-step.