Design of Power Efficient Stable 1-Bit Full Adder Circuit

Shahmini Subramaniam; Ajay Kumar Singh; Gajula Ramana Murthy

doi:10.1587/elex.15.20180552

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Design of Power Efficient Stable 1-Bit Full Adder Circuit

Shahmini Subramaniam, Ajay Kumar Singh, Gajula Ramana Murthy

著者情報

キーワード: Power efficient, Pass Transistor Logic (PTL), 1-bit full adder circuit, MC (Monte Carlo) simulations, Reliability

ジャーナルフリー早期公開

論文ID: 15.20180552

DOI https://doi.org/10.1587/elex.15.20180552

この記事には本公開記事があります。

The final version of this article is now available: Vol. 15 (2018), No. 14 pp. 20180552-20180552

詳細

抄録

This paper presents design of 14-T 1-bit full adder power efficient Pass Transistor Logic (PTL) based stable circuit. Due to compact architecture, power consumption is low and response is faster. MC (Monte Carlo) shows that the circuit is more reliable against any statistical variations.

責任著者(Corresponding author)

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