Non-floating and Low-power Adiabatic Logic Circuit

抄録

This paper proposes a new adiabatic logic. Adiabatic logic is a good method to reduce power consumption. Several common adiabatic logics suffer from floating output which results in lack in robustness, by using the periodic power supply. At first, we analyze the floating phenomenon of previously proposed 2PC2AL in this paper. The proposed adiabatic logic can prevent the floating of the nodes to add two logic switches between the power supply and charging-discharging transistor. This paper also reports a comparison of energy dissipation between the different adiabatic logics such as, ECRL, 2N2N2P, 2PASCL, 2PC2AL, and the proposed circuit. In the SPICE simulation, the target application is a 4-bit multiplier for IoT products. Through the simulation, the output of the proposed circuit with cascade connection has a stable function.