Reconfigurable hardware architecture for Mean Level and log-t CFAR detectors in FPGA implementations

抄録

For radar target detection, the selection of the optimal constant false alarm rate (CFAR) detector usually relies on clutter distribution types. By integrating two types of Mean Level and log-t CFAR detectors, a reconfigurable hardware architecture is proposed and implemented on field programmable gate array (FPGA). It allows to switch a suitable detector for specific clutter distribution and configure the parameters including the number of reference and guard cells, the threshold factor, and the desired false alarm probability. Synthesis results reveal its advantages of occupying 18% less hardware resources than the architecture that naively integrates two types of detectors. According to the experimental results, the proposed architecture can perform a processing speed of 100 MHz and require only 83 microseconds for a clutter of 8192 samples.