A 54-GHz 23.3%-PAE CMOS Power Amplifier Using Dual-Gated Transistors

抄録

A 54-GHz two-stage pseudo-differential common source power amplifier (PA) is implemented using dual-gated transistors (DGT). DGT structure is able to enhance both the linearity and back-off efficiency without consuming extra dc power. The nonlinear characteristics of the transistor can be compensated by adjusting the gate width and overdrive voltage of each transistor in the DGT. Besides, the dc power consumption of the DGT amplifier scales with the amplitude of the input signal, resulting in enhanced PAE at back-off. Fabricated in a 65-nm CMOS process, the measured small-signal gain of the 0.5×0.98 mm² PA is 17 dB at 52 GHz while consuming 24 mW from a 1-V supply. The maximum saturated output power is 10.5 dBm with a peak PAE of 23.3% measured at 54 GHz; the measured output power and PAE at 1-dB compression is 7.6 dBm and 17%, respectively.