A Second-Order Feedforward VCO-Based ADC with Continuous-Time Sigma-Delta Modulator for EEG Signal Recording Front Ends

Abstract

This paper presents a VCO-based second-order feedforward CT-ADC architecture designed for EEG recording front-ends. This structure permits the first-stage integrator to process only the quantization noise, thereby enhancing its linearity. A dead-band switch and gain stage are added between the input and DAC feedback ends, effectively reducing the ripple effects caused by chopping and the noise introduced by feedforward. To validate the proposed architecture, an ADC was fabricated using a 65 nm CMOS process, achieving an SNDR of 84.5 dB, a DR of 94.6 dB within a 10 kHz bandwidth, and the smallest chip area of 0.026 mm². The ADC consumes 7.22 µW of power from a 1 V supply, achieving an SNDR performance value (FoM) of 175.9 dB for the VCO-based ADC.