論文ID: 21.20240239
In this study, a novel noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) architecture is proposed, incorporating a noise transfer function (NTF) strengthening method (NSM). The order of NTF is strengthened by using an extra capacitive digital-to-analog converter (CDAC) and a cascaded Finite Impulse Response-Infinite Impulse Response (FIR-IIR) filter. The prototype converter uses an 8-bit split capacitor CDAC. The NSM is implemented on an NS SAR ADC in 40nm process technology, achieving an Effective Number of Bits (ENOB) of 16.6 bits at an effective bandwidth of 200 kHz with an oversampling ratio (OSR) of 32 and has been validated over process-voltage-temperature (PVT). The proposed ADC consumes 1.32 mW at a 1.1V supply voltage which occupies an active area of 0.0903 mm2. The Schrier figure-of-merit (FoM) of 182.8 dB is obtained.
