A High-Throughput Hardware Architecture for Bilateral Filter with Configurable Convolution and Cost-Effective MAC Unit

抄録

The bilateral filtering algorithm has broad application in image denoising. However, its complex computational and high bandwidth requirements for image data transmission have been limiting factors in its processing speed. This brief presents a high-throughput hardware architecture designed for the bilateral filtering algorithm, supporting images of arbitrary resolution and three convolution window sizes. This architecture reduces the computational through approximation calculations and enhances throughput for high-definition image processing via a data prefetch strategy. Additionally, we introduce a cost-effective MAC unit that minimizes critical path delays and area consumption. In terms of hardware implementation, even on a low-cost Xilinx Zynq-7000 FPGA platform can process 1024×1024 resolution images at over 160 frames per second, with a maximum working frequency of 192 MHz.