A 13-bit 200-MS/s separated kT/C noise canceled pipelined SAR ADC with hybrid dynamic amplifier

Abstract

This paper presents a 13-bit, 200-MS/s, two-stage pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) with separated kT/C noise cancellation and a hybrid dynamic amplifier (DA). The proposed architecture employs a coarse SAR to decouple the kT/C noise cancellation from the first-stage conversion, thereby significantly reducing both the excessive power consumption and the additional noise introduced by amplifier operation during this process. With a DA reused for kT/C noise cancellation and the first-stage residue amplification, dynamic noise suppression can be effectively achieved. In order to meet the inter-stage gain and linearity requirements, an open-loop inverter-based DA with tunable harmonic distortion cancellation is utilized as the second-stage residue amplifier. Designed in a 55-nm CMOS process, the proposed ADC achieves a 73.8 dB SNDR with 0.021 mm² core area, and has a power consumption of 1.9 mW at 200 MS/s. This yields a Schreier figure of merit (FoM) of 181 dB and a Walden FoM of 2.37 fJ/conversion-step.