20nm MOSFETにおけるソース・ドレイン抵抗の電気特性パラメータへの影響

抄録

In this work, the effects of source and drain resistances (R_S, R_D) on device characteristics are investigated for sub-20nm MOSFETs. The current driving capability is calculated for several structures such as planar bulk, SOI, and Multi gate MOSFETs by using the ITRS data. It is found that the degradation of the drain currents due to R_S and R_D becomes significant as the gate lengths are scale down to sub-20nm region. In order to investigate the effects of R_S and R_D on the device parameters such as the channel length modulation coefficient λ and the saturation drain current I_DSAT, the drain currents are simulated by using the circuit simulation. The intrinsic MOSFET model parameters were extracted from the experimental I_D-V_D characteristic of 20nm nMOSFET. The source and drain resistances are changed from 0 to 100 ohm. It is found that the degradation of I_DSAT due to R_S and R_D shows the linear gate voltage dependence. For the long channel MOSFET, the degradation of λ shows the linear gate voltage dependence. On the contrary, for the short channel MOSFET, the degradation of λ shows the little gate voltage dependence.