抄録
In this paper, the architecture for high-sensitivity and wide-range CMOS temperature sensor circuits is presented. The proposed architecture consists of the PTAT circuit with the positive slope, the PTAT circuit with the negative slope and a subtractor. The concrete circuit based on the proposed architecture is designed, and evaluated through HSPICE with a set of device parameters of 0.18μm CMOS process. The simulations demonstrate a maximum temperature error of 2.3°C and the maximum current consumption of 28.7μA under the condition that the temperature range is from -20°C to 100°C, the sensitivity is 5.2mV/°C and VDD=1.5V.
