抄録
Recently, the number of electronic devices handling confidential information has increased. In these devices, cryptographic circuits are applied to protect the confidential information. It has been sufficiently confirmed that the decryption of the encryption standards used in cryptographic circuits is computationally impossible. However, it was recently reported that when a theoretically safe encryption algorithm was embedded in the hardware, confidential information could be illegally specified by fault analysis attacks. Here, fault analysis attacks specify the secret keys by intentionally generating a fault during the encryption processing and by comparing the fault and normal cases. Almost all previous studies have strictly constraints related to the number of faults and the position of faults. Therefore, this study proposes a new fault analysis attack which has no constraint for the number of faults and considers the architecture. Experimental results using FPGA show the validity of the proposed attack.
