Recently, the threat level of power analysis attacks has been raised. Power analysis attacks acquire confidential information from cryptographic circuits that are embedded in hardware, such as credit and cash cards, by analyzing their power consumption. Therefore, it is important to secure resistance against power analysis attacks. This study proposes a new power analysis attack method that can be used to improve the efficiency of the resistance evaluation of cryptographic LSI. The proposed method performs power analysis not in the conventional time domain but in the frequency domain. Moreover, it uses a partial key that is specified through the use of conventional power analysis attack to estimate other partial keys. Compared with resistance evaluation that uses typical attack methods, the proposed method reduces the computational amount required for resistance evaluation greatly while maintaining the attack accuracy. The validity of the proposed method is verified through evaluation experiments performed with the use of a cryptographic circuit implemented on FPGA.
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