A Proposal for Downconverting A-to-D Converter Based on Even-Harmonic Mixer and ΔΣ-TDC

抄録

A novel architecture of downconverting A-to-D Converter is proposed, which is based on even-harmonic mixer and ΔΣ Time-to-Digital Converter. Analog circuits are minimized by the proposed architecture. As a design study, a test chip of 200 MHz RF signal to baseband downconverter is designed and fabricated. The design uses a standard 0.18 µm CMOS technology, and the simulation results verify the operation of the proposed architecture. Measurement result is presented and it verified the functionality of the fabricated test chip.