部分最適化を用いたコンパレータ回路の自動設計の高速化

抄録

Automatic design of analog integrated circuit is in great demand due to the requirement of the reduction of design time. Optimization algorithms are often used for the automatic design. However, because the optimization algorithm is based on the stochastic method and determines the circuit parameters at random, a lot of circuits which do not operate in principle are generated and simulated to find the optimal circuit. These redundant simulations consume time in vain. In this paper, the automatic design method, which achieves to reduce the redundant simulations, of the topology and element values of the comparator circuit, is proposed. For the decision of the topology, simulation results are utilized to determine the topology, which results in the reduction of numbers of simulations. For the decision of element values, Divided Circuit Optimization which performs optimization for each function block is proposed. The reduction of the optimization target means that HSPICE optimization function ensures to converge. Compared with the conventional method, the proposed method can reduce numbers of simulations to 1/30 and simulation time to 1/3.