A Basic Study on Defect Inspection Method for ASIC Manufacturing Lines

Abstract

Since strict defect control causes both the enhancement of manufacturing yield and the drop of machine operation rate, defect inspection paremeters should be optimized to minimize the production time for a fixed amount of ASIC chips. We propose new manufacturing model which takes account of not only inspection and yield model but also and workflow model. In this paper, as a first step, we study basic characteristics of our model affected by inspection conditions, defect situations and workflow conditions. The numerical experimental results demonstrated that many phenomenon can be calculated only by the model which takes account of both yield and workflow. For an example, control limit of defected die count should be increased about 50% when loading factor chages from 60% to 85%.