Chip Layout Optimization of SiC Power Modules Based on Multiobjective Electro-Thermal Design Strategy

抄録

Electro-thermal co-design of power modules is required to maximize the capabilities of promising power semiconductor devices. The chip layout on the substrate, which is restricted by the size of the power module substrate, determines the electrical and thermal characteristics of the power module. This paper proposes a chip layout optimization strategy for power modules based on a multiobjective electro-thermal design algorithm. The parasitic inductance and thermal resistance of the SiC power module are evaluated using the unified simulation model based on the multiphysics solver of the finite element method. The proposed multiobjective optimal design approach uses non-dominated sorting genetic algorithm II (NSGA-II) and the developed simulation model to obtain a Pareto front for the parasitic inductance and thermal resistance of the power module. Module samples with the obtained Pareto front parameters are experimentally characterized and validated with numerical simulation results.