A New Variant of Sparse Approach for Fast Power Flow Computation Employing Pipe Lined Processor

抄録

This paper presents a new variant of sparse approach for fast power flow computations. The proposed approach features a new and fast node ordering scheme, the realization of an index search operation (usually involved in LU decomposition) only once by shifting it out of the iterative loop of Newton-Raphson (NR) based power flow computation, the adoption of static and simple data structure, and the implementation detail designed to extract the advantage of pipe line feature. The proposed approach is tested using a single chip pipe lined processor, called as Digital Signal Processor (DSP) and is found to suit well to this type of processors. The DSP is made operative by using personal computer (PC) as its host and the whole system is named as DSP system. For the several test systems considered, the complete job of performing power flow computation is assigned to DSP only. The significant reduction in the computational efforts with the proposed sparse variant over conventional approach is obtained while the computing time is observed to vary linearly with the change in system size.