3-D Stacking of Silicon Components using Micro-Electro-Mechanical System (MEMS) Technologies

Abstract

Conductive interconnection through Silicon (Si) substrate has been required as one of the essential elements for high-density packages, module assemblies and/or system integration for many years. In this paper, we demonstrated to form metal filled Through-Holes (THs) from the front to the back of thick Si wafer (∼500 μm) by Optical Excitation Electro-polishing Method (OEEM) and Molten Metal Suction Method (MMSM). The conductive interconnections through thick Si substrate formed by the both technologies have more than 500V dielectric breakdown voltage of insulator between the Si substrate and the filled metal and leakage free structure between the front and the back of the substrate. In our experiments, 3,500THs/mm² were formed in a thick Si substrate, and Sn was filled after the formation of insulation layers in the THs. These metal filled THs can be applied for Si terraces, Si Optical Bench (SiOB), 3D-stacked IC or other System In Package (SIP). In addition, water glass bonding is proposed as a low temperature and stress free sealing technique for the 3D-stacking IC fabrication.