周波数同期型発振回路の時間分解能を利用した1.2 V, 15.8ビット容量-デジタル変換IC

抄録

In this paper, we propose a new architecture for Capacitance-to-Digital convertor. We clarified the configuration that utilizes the time resolution of the frequency-Locked-Loop oscillator using a switched capacitor that enables stable operation, and integrated the circuit using 0.18µm standard CMOS technology. As a result, a power supply voltage of 1.2V, a capacitance resolution of 15aF, ENOB of 15.8bit, high resolution, and wide dynamic range conversion characteristics were achieved.