抄録
The purposes of this paper are (a) using Taguchi method to search for optimal fitness value and (b) evaluating the power and signal delay of logic blocks in circuit design to get an optimum circuit in complexity, power and signal delay. Results are obtained for 2-bit full adder circuit of 5*5 arrays. The overall objective is to discover novel solutions by the application of GA-PSO in the circuit design optimization process. Our proposed design method is applied to more complex and larger circuits, so that enhance exact information on circuit to fitness function is successfully obtained.
