抄録
In recent years due to the complexity and large-scale in the embedded system, it has become general to add a hardware accelerator to the CPU. But, since these hardware accelerators are developed for each software and determined specifications in the early development stage, must also be redesigned accelerator at the time of renewal and change of software. This leads to an increase in the development cost and extension of the development time.Therefore, we propose a virtual CGRA configured on the FPGA, and work the development of reconfigurable accelerator that freely modifiable circuit configuration.
