MECデバイス用FPGA-IP試作チップの静的タイミング解析の評価

抄録

Our lab develops an FPGA-IP prototype chip for MEC devices. One of the changes made from the first prototype named TEG1 to the second prototype chip named TEG2 was to incorporate hard macros dedicated to adders and multipliers into the FPGA architecture of TEG1. The reason for this change is to solve issues such as resource usage and delay constraints that are necessary when implementing additions and multiplications used in applications. In this paper, we report the evaluation results of his TEG2 compared to his TEG1 by a static timing analysis.