抄録
The present study was concerned with the grain size and the boundary layer properties of (Sr, Ca) (Ti, Nb)O3 based ceramics which were applied for capacitive-varistor devices. The results were summarized as follows: (1) The addition of SiO2 resulted in making same average grain sizes both of A-site excess and B-site excess- (Sr, Ca) (Ti, Nb)O3 based semiconductive ceramics, which had appreciably different ones without SiO2 addition, (2) A liquid phase sintering was considered to be the case with SiO2 both of A-site and B-site excess samples from the TEM observations, (3) SiO2 addition promoted a reproducible varistor effect even after 1 mA current flow, (4) Insulator composition with Bi2O3 to form the insulated boundary layer showed the occurrence of lower varistor coefficients, α<6. Bi2O3, which has been widely used for the capacitor, was not necessary to add the varistor property.
