Fabrication of Multi-stacked Integrated Circuit for High-Performance Image Sensors

Naoki Nakatani; Yuki Honda; Masahide Goto; Toshihisa Watabe; Masakazu Nanba; Yoshinori Iguchi; Takuya Saraya; Masaharu Kobayashi; Eiji Higurashi; Hiroshi Toshiyoshi; Toshiro Hiramoto

doi:10.5104/jiepeng.13.E20-004-1

Short Note

Fabrication of Multi-stacked Integrated Circuit for High-Performance Image Sensors

Naoki Nakatani, Yuki Honda, Masahide Goto, Toshihisa Watabe, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

著者情報

Naoki Nakatani
Science and Technology Research Laboratories, NHK
Yuki Honda
Science and Technology Research Laboratories, NHK
Masahide Goto
Science and Technology Research Laboratories, NHK
Toshihisa Watabe
Science and Technology Research Laboratories, NHK
Masakazu Nanba
Science and Technology Research Laboratories, NHK
Yoshinori Iguchi
Science and Technology Research Laboratories, NHK
Takuya Saraya
Institute of Industrial Science, The University of Tokyo
Masaharu Kobayashi
Institute of Industrial Science, The University of Tokyo
Eiji Higurashi
National Institute of Advanced Industrial Science and Technology
Hiroshi Toshiyoshi
Institute of Industrial Science, The University of Tokyo
Toshiro Hiramoto
Institute of Industrial Science, The University of Tokyo

キーワード: 3D Integrated Circuit, CMOS Image Sensor, Hybrid Bonding, 3D Ring Oscillator, More-than-Moore

ジャーナルフリー

2020 年 13 巻 p. E20-004-1-E20-004-3

DOI https://doi.org/10.5104/jiepeng.13.E20-004-1

詳細

抄録

We have been developing a three-dimensionally (3D) structured complementary metal-oxide semiconductor (CMOS) image sensor (CIS), which has individual signal processing circuits in each pixel under the photoelectronic conversion area for high-performance and multi-functional operation. In this paper, we report on our experimental 3D integrated circuits developed using multi-stack technology, which enables us to fabricate 3D-CISs with small pixels. The results showed the fundamental operation of the prototype circuit, which indicates the feasibility of highly integrated 3D-CIS of More-than-Moore type applications.

責任著者(Corresponding author)

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