Transactions of The Japan Institute of Electronics Packaging
Online ISSN : 1884-8028
Print ISSN : 1883-3365
ISSN-L : 1883-3365
Short Note
Low Temperature SLID Bonding Approach in Fine Pitch Chip-stacking Structure with 30 μm-pitch Interconnections
Chao-Jung ChenYu-Min LinTzu-Hsuan NiTao-Chih ChangHan-Tang HungChin-Hao TsaiC. Robert KaoChang-Chun Lee
著者情報
ジャーナル フリー

2020 年 13 巻 p. E20-010-1-E20-010-4

詳細
抄録

In this study, a 160°C low-temperature bonding method was developed for fine pitch chip-stacking application by Solid-Liquid Inter-diffusion (SLID) bonding technology. The chip-to-wafer test was conducted by using Cu/Sn-Ag and Cu/Ni/In as the micro pillar bump structure for top chip and bottom wafer, respectively. Indium, with a low melting point of 157°C, was chosen to realize the SLID bonding mechanism in this study. A thin indium layer with a thickness of 1 μm was plated on nickel to induce low temperature bonding with tin. These 30 μm-pitch interconnects bonded at low temperature were well-bonded and exhibited excellent electrical continuity through 3,264 I/Os. Furthermore, the bonded samples were tested under reliability assessments to verify the thermal stability.

著者関連情報
© 2020 The Japan Institute of Electronics Packaging
前の記事 次の記事
feedback
Top