Abstract
We successfully developed a novel methodology for the electrical design of the embedded-large scale integrated circuit (LSI) package used as the bottom package of Package-on-Package (PoP) structures. The developed methodology enables an existing chip with a peripheral pad layout for wire-bonding to be embedded into the organic interposer substrate. The key concepts of the methodology are a "grid-type" via layout surrounding the embedded LSI and the "signal-center" pad re-arrangement by using redistribution layer (RDL) on the embedded LSI. These concepts help reduce the bottom package thickness by 60%, as compared to a conventional non-embedded-type package. We also demonstrated the effectiveness of the proposed methodology by fabricating PoP structures designed with these concepts. As well as complete device operations, the signal and power integrity of the developed PoP demonstrated better properties than those of the conventional PoP structure. This approach would essentially be cost-effective and useful, especially for set vendors, because expensive chip redesign is eliminated.
