Wire bonding is a key technique for electrical interconnections between integrated circuit (IC) and the metal frame or printed circuit board (PCB). One of the most common wire bonding system is bonding of the Au wire to Al metallization, however, Cu wire is being considered as replacement for Au wire due to surge of Au price. This research focuses on the formation and growth behavior of Cu/Al intermetallic compounds (IMCs). In order to investigate IMC growth after 30, 60 and 120 min of aging at 270, 300 and 330°C, cross-section of Al, Cu and Cu/Al IMCs were examined by scanning electron microscopy (SEM). The results showed that the consumption of the Al layer is more rapid than that of Cu layer, and that after 120 min at 330°C the Al layer is entirely consumed. The formation of three distinct Cu/Al IMC layers was observed. Scanning transmission electron microscopy (STEM)/energy-dispersive X-ray spectroscopy (EDS) was used to identify the three IMC layers formed at the interface. In addition, the IMC compositions were identified by selected-area diffraction pattern (SAD). These were CuAl, Cu3Al2 and Cu9Al4. Also, the activation energies of Cu/Al IMC growth were obtained from an Arrhenius plot.
In this study, we evaluated the ultrasonic vibration energy required for Cu-Cu bonding using flip-chip bonding technology in air atmosphere. The transmissibility of the ultrasonic vibration was assumed to be different in bump structures with high or low stiffness values. Therefore, we investigated the bonding strengths of Cu bumps with different aspect ratios (bump heights of 5 μm, 20 μm, and 40 μm). As a result, we found that the 20 μm-high Cu bumps were properly bonded with sufficient bonding strength by comparison with the other bumps. No significant voids that decrease the bonding reliability were present at the Cu-Cu interface of well-bonded Cu bumps. In addition, coplanarity between the bonding head and the stage surface was found to be an important factor for ultrasonic bonding, because it enabled all bumps to start to bond simultaneously.
We investigated the electrical characteristics of the power supply path, which are influenced by the via structures in the build-up substrate. The build-up substrates are composed of core layers and build-up layers, connected by the plated through hole (PTH), and the build-up via (BU via), respectively. This paper investigates how the BU via structures affect the power supply path, and discusses the design constraints of the via structures in the build-up layers. Three design constraints were considered for the build-up substrate, which comprises six build-up layers laminated on both sides of the core layers. The first constraint limits the BU via stack number, the second is the propriety of the BU via stack on the PTH, and the last limits the number of BU vias connected on the PTH. By changing these design constraints, the power supply paths were designed and compared by simulation and measurement. As a result, the proposed via structures had a significantly difference in terms of resistance and inductance of the power supply path. We have found a via structure that improves the electrical characteristics while also yielding good connectivity and productivity.
In this article an IGBT package is measured using thermal transient test method following JESD 51-14 standard. In order to study the thermal structure in the package, a detailed CFD (Computational Fluid Dynamics) simulation model is also created and calibrated against the physical device using structure function. By the calibrated CFD model the package’s thermal behavior is studied. The purpose of this paper is to illustrate the process of calibrating CFD model to get a "thermally identical" representation of physical devices.
Effects of filler content and coupling agent on mechanical properties of underfill (UF) were investigated using standard UF materials which are composed bisphenol F-type epoxy resin and spheroidal SiO2 filler. For the effect of filler content, elastic modulus of UF increased and fracture strain decreased with increasing the filler content. On the contrary, the effect on tensile strength was negligible. When the temperature was above Tg, elastic modulus decreased and fracture strain increased remarkably. Fracture mainly occurred in matrix resin below Tg and in the interface between matrix resin and filler above Tg. Moreover, it was confirmed that tensile strength and fracture strain were decreased by aging treatment. For the effect of coupling agent, elastic modulus and tensile strength of UF were increased by coupling treatment. Fracture strain was increased at R.T., but was decreased at 80°C and 120°C by coupling treatment. Tensile strength depends on the interfacial state of matrix resin and fillers. Peeling of fillers from matrix resin was suppressed by coupling treatment at the temperature under 80°C. Fracture mode of UF with coupling treatment changed from matrix fracture to interfacial fracture in the boundary of Tg.
To provide the basic considerations for EM radiation from practical asymmetrical differential-paired lines with bend routing, this paper newly attempts to propose locally shielded differential-paired lines for establishing SI performance and suppressing imbalance component and EMI generated by differential-paired lines with bend (called as turnoff point) discontinuities. The conductive plane is placed on discontinuity region asymmetrically. The concept of locally shielded layout is based on compensation of phase-difference due to the bend discontinuities, by using electric-coupling between signal trace and a conductive plane for the shield. The proposed method is suitable for implementing on PCB, without changing layout of the differential-paired lines. To compare the effect of the locally shielded paired-lines on CM component, the |Scd21|, which is defined as the conversion from DM to CM, are evaluated. The significant suppression effectiveness of |Scd21| in the case study is achieved below 1 GHz by locally shielded differential-paired lines. Consequently, the validity of the proposed locally shielded layout is demonstrated. It is demonstrated that the proposed locally shielded layout is suitable for improving the SI performance and suppressing the CM in the case study. This study has successfully reported the basic method for suppressing imbalance component of differential-paired lines with bend discontinuities.
We report a varifocal lens made of potassium tantalate niobate (KTa1−xNbxO3, KTN) that exhibits a huge second-order EO effect, namely the Kerr effect. The lens consists of a KTN block on which four strip film electrodes are mounted. A voltage applied with these electrodes forms an electric field distribution, modulates the refractive index of the KTN block, and bends light rays. The lens power can be controlled from zero to 1.4 m−1. By inserting the KTN lens in front of a fixed glass lens with a focal length of 250 mm, we were able to move the focus by 87 mm. It was confirmed experimentally that the focus of the lens moved as theoretically predicted while still maintaining a response time less than 2 μs. Owing to the anisotropy of the Kerr effect, the lens is polarization dependent. We also present a technique for eliminating this dependence.
The success of smart optical interconnects for practical use strongly depends on the development of sophisticated coupling technologies that can achieve both high coupling efficiency and easy alignment. One promising technology for solving these problems is the fiber self-written waveguide (SWW) method, which uses light-curable resin. We fabricated a micro-scale 90° light-path converter on the top of mechanically transferable connector that enables smart connection between fibers and an optical wiring board. Then, building upon this fiber SWW technology, we devised a new technology called the mask-transfer SWW method. By applying this technology, we developed a new polymer V-groove fabrication method, which enables V-grooves to be formed at designated positions to facilitate coupling between fibers and devices.
This paper describes the effect of cooling performance from the bottom surface of power Si MOSFET on thermal properties of power Si MOSFET with electro-thermal analysis. Generally, the bottom surface is assumed to be 350 K as boundary condition in calculations to obtain thermal properties of power Si MOSFET. However, in fact, the bottom temperature is not always constant, and the temperature is depended on the cooling performance. And the bottom temperature is important factor on investigation of a temperature distribution of power Si MOSFET. Therefore, in this study, we investigate the effect of the variation of the cooling performance on the temperature distribution of power Si MOSFET with electro-thermal analysis. The results show, when the heat transfer coefficient is more than 5 × 107 W/(m2·K), the bottom temperature is about 300 K. Further, the variation of the hot spot temperature with respect to the bottom temperature is almost linear.
Nowadays, thermal flow simulation based on computational fluid dynamics (CFD) is applied to the thermal design of electronic equipment. In this paper, we discuss the applicability of the multiple reference frame (MRF) approach, which is a new method for modeling an axial cooling fan, to the thermal flow simulation of electronic equipment using the CFD code. In this study, as the first step, flow visualization of the exhaust air flow pattern of the experimental axial fan was conducted. Then the flow visualization results were compared with the MRF fan model simulation results. Finally, the P-Q characteristic obtained by MRF fan model simulation was compared with the measured P-Q characteristic to validate the applicability of the MRF approach to the thermal flow simulation of electronic equipment.
This paper describes power generation enhancement in a millimeter-sized slit-and-slider structure in an electrostatic vibrational microelectromechanical-system (MEMS) device for energy harvesting. To increase current generation, we have developed a new method to narrow the gap between movable and fixed electrodes for energy conversion in a limited size. The device is fabricated with a nested flip-chip assembly technique. This method can achieve a micron level gap narrowing of 3.8 μm. The approach greatly increased the power generation to 2.3 nA with a 1 mm2 movable part in a slit-and-slider structure. The structural normalized power generation having the gap of 3.8 μm is 8.83 times larger than the previous one.
We report a multilayered Sn/Ag3Sn film electroplated on Cu alloys with high reliability as promising coating materials for LED lead-frames and for electric connectors. The multilayered Sn/Ag films consisted of an Ag-Sn alloy film with 30-80 nm-thick as Ag3Sn phase covered on a 1 μm-thick Sn film on Cu alloy substrates. The as-deposited Sn/Ag3Sn films exhibited a high specular reflectivity around 70% at the wavelengths of 480 nm, which was lower than a commercial bright Ag film with total reflectivity of 90% but much higher than a commercial bright Au film in 24% at the same wavelength. It was found through an accelerated sulfuring test that, the reflectivity of the Sn/Ag3Sn films was almost unchanged even after immersing in a 0.2% (NH4)2Sx solution for 60 min, compared to the abrupt decrease to 15% for the conventional Ag film even after immersing for 10 min. The excellent sulfuring resistance and durability of the multilayered Sn/Ag3Sn films can be attributed to the existence of a stable SnO2 film existed on the surface of Ag3Sn alloy, which was revealed by a UPS analysis in a vacuum chamber by heating at 473-673 K, thus protecting underneath Ag3Sn alloy film and inhibiting the chemical reaction of Ag and S2− ions.
The flip-chip ball-grid array (FCBGA) package has been applied in the fields of high-end server and network systems to achieve high performance in data processing. The demand for high-speed data processing in the global IT network and cloud markets has also continued its rapid expansion in recent years, so there is a strong need for the further development of FCBGA packages with high performance in response. We have developed a flip-chip technology with Cu-pillar bumps at a very fine staggered pitch of 30 μm, utilizing non-conductive paste (NCP) resin to adapt the package for use with devices having large numbers of pins, at least some of which carry high-speed signals. The keys to this flip chip technology are optimizing the conditions for the reaction of the NCP resin under the die and the effect of melting the solder when making connections. The effectiveness of different heights for the solder joints was studied to confirm the reliability of the package, and the results and a description of the technology are reported in this paper.
A multi-channel hybrid integrated light source using a novel spot-size converter with a SiOx slab layer for a wide fabrication margin has been developed that has high output power uniformity. The configuration of the light source was optimized to minimize power consumption by considering of the thermal interference between the channels in a laser diode (LD) array and also between the LD array chips. On the basis of the optimization, a 1,000-channel light source was demonstrated to have an over- 10-Tbit/s bandwidth optical interconnection. The hybrid integrated light source should be easily adaptable to a photonics-electronics convergence system for ultra-high-bandwidth interchip interconnections.
We successfully developed a novel methodology for the electrical design of the embedded-large scale integrated circuit (LSI) package used as the bottom package of Package-on-Package (PoP) structures. The developed methodology enables an existing chip with a peripheral pad layout for wire-bonding to be embedded into the organic interposer substrate. The key concepts of the methodology are a "grid-type" via layout surrounding the embedded LSI and the "signal-center" pad re-arrangement by using redistribution layer (RDL) on the embedded LSI. These concepts help reduce the bottom package thickness by 60%, as compared to a conventional non-embedded-type package. We also demonstrated the effectiveness of the proposed methodology by fabricating PoP structures designed with these concepts. As well as complete device operations, the signal and power integrity of the developed PoP demonstrated better properties than those of the conventional PoP structure. This approach would essentially be cost-effective and useful, especially for set vendors, because expensive chip redesign is eliminated.
2.5D packages that utilize an interposer capable of fine patterning are gaining prominence for applications that require high data transmission rate, wide I/O bus, and higher integration of functionality. There are various interposer materials proposed such as silicon, glass, and organic. Silicon has high thermal conductivity compared to glass and organic. The authors studied thermal performance of Si interposer flip chip plastic ball grid array (FCPBGA), glass interposer FCPBGA and conventional multi chip module (MCM) FCPBGA assuming that a high power logic chip and a low power memory chip are packaged in each package configuration. Computational fluid dynamics (CFD) was used to analyze thermal performance of each package with the variation of cooling option - lidless, lidded and heat-sink-attached-on-lid. The effects of airflow rate and power consumption of logic chip were also analyzed in this study.
This study describes a possibility of a pulsating airflow for an application to electronics cooling. Forced convection cooling by using fans is the most common strategy for dissipating heat from electronic devices. In high-density packaging electronic equipment, flow separation of the airflow decreases cooling performance of electronic components. In order to suppress the decrease of the cooling performance, we are now focusing on a generation of pulsating airflow. The flow separation around the electronic components may be inhibited by the airflow pulsation and the cooling performance rear the components may be improved. The pulsating airflow may be generated easily by controlling the input power of the cooling fans. However, in order to apply the pulsating flow to the cooling method of electronic equipment, whether the pulsating flow can enhance the cooling performance around the heating components or not should be clarified. In this study, we experimentally investigated a cooling performance of a pulsating airflow around a cylindrical block that simulates electronic components. The pulsating airflow gave almost the same heat transfer performance as the steady airflow that the time-averaged flow rate was smaller than that of the pulsating flow. The pulsating flow may become the effective cooling method for next generation electronic equipment which can decrease the power consumption of the cooling fans while maintaining the cooling performance of the electronic components.
Advanced vertical interconnect technology that combines traditional HDI structures feature micro-vias and conductive paste-vias was developed to fabricate multilayer PWB, owning excellent electrical performance, mechanical reliability and mass productivity at reasonable cost. This advanced multilayer PWB is constituted of high elastic modulus thermosetting dielectric composition (Glass epoxy (FR-4)) with interstitial via holes and/or Cu micro-vias, and sintered conductive paste-vias buried in low elastic modulus thermosetting dielectric composition. The latter composition properly act as mechanical buffering layer of vertical interconnection between upper and lower multilayer PWB. The first in this paper, manufacturing process condition was discussed the optimum electrical performance at the interface of HDI Cu lands and conductive paste with interposing low elastic modulus dielectric material was achieved. Next, the micro structure and sintering condition at the interface of conductive paste and HDI Cu land was observed and analyzed by using SEM and EDX. In addition, mechanical reliabilities, estimated by applying structural analysis method, and signal transmission properties by way of this buried conductive paste, analyzed by frequency and time-domain simulation, were discussed. From these results, it was found that this advanced vertical interconnect technology with sintered conductive paste and low elastic dielectric shows sufficient mechanical reliability and electrical property for passing high-speed signal up to 15 Gbps.
In this paper, we introduce a method to measure the resistance of high density post-bond Through Silicon Via (TSV) including serial micro-bumps and bond resistance in Three Dimensional Stacked IC (3D-SIC). The key idea of our technology is to use Electrical Probes embedded in stacked silicon dies. It is a measuring circuit based on Analog Boundary-Scan (IEEE 1149.4). The standard Analog Boundary-Scan structure is modified to realize high measuring accuracy for TSVs in 3D-SIC. The main contribution of the method is to measure the resistance of high pin count (e.g. >10,000) post-bond TSVs accurately. Electrical Probes correspond to the high density of TSV (e.g. < 40 um pitch) and work like Kelvin probe. The measurement accuracy is less than 10 mΩ. We also introduce the preliminary results of small scale measuring experiments and the results of SPICE simulation of large scale measuring circuits.