抄録
We believe that personal robots like current personal computers will be used in an office and at home in the near future. And we have already designed function-classified parallel computer architecture for personal robots: ASPIRE (ASynchronous, Parallel, Interrupt-based, and REsponsive architecture) . In this paper, we design and implement the personal robot ASPIRE-II based on ASPIRE using RISC processors. Many researchers think that RISC processers are not suitable for embedded application due to the pipeline hazards, and the loads and stores of a large number of registers in case of interrupts. However we dare to apply RISC prosessers (SPARC family) to ASPIRE so as to have both high computing performance and good interrupt capability. Definitely, we apply register windows of SPARC architecture to ASPIRE. We also describe the efficiency of the architecture by evaluating ASPIRE-II.
