日本計算工学会論文集
Online ISSN : 1347-8826
ISSN-L : 1344-9443
ペナルティ法を用いたGAによるチップマウンタシステムの戦略的実装時間最適化
宮嶋 隆司中村 正行小林 光征小杉 俊
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ジャーナル フリー

2002 年 2002 巻 p. 20020018

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This paper presents an optimization method of production efficiency about the placement time in the chip mounter system under one constraint. This constraint is that an operator specifies a chip mounter which has minimum placement time. Placement time changes greatly by the performance of the chip mounter and the configuration of the system. The problem is how to distribute parts and parts feeders to each chip mounter. We propose a distributing method by GA adopting the penalty method. Several numerical experiments about some systems composed of more than one chip mounter with different performance were done. It was confirmed that our proposed method had validity more than conventional method through the results of numerical experiment. Furthermore, those characteristics and validity are explained about the GA adopting simple penalty method (SPM-GA) and the GA adopting improved penalty method (IPM-GA) that a penalty is changed one after another with the progress of the generation.
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© 2002 The Japan Society For Computational Engineering and Science
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