THE IMPACT OF IC DESIGN-FOR-TEST ON TIME-TO-MARKET

抄録

In the changing VLSI test environment, this paper re-examines the VLSI Test development trade-off of quality, cost of Test development and Time-to-Market. The paper looks at what technology has been available in the recent past and is currently available to reduce Time-to-Market in terms of Design-for-Test, the types of Test, and automation possibilities. Finally it briefly looks at future opportunities for the contribution of VLSI Test to the reduction of Time-To-Market for a VLSI chip.