IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Fabrication of Superconductor Devices; Key Technology in Superconductor Electronics
Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
Shuichi NAGASAWAMasamitsu TANAKANaoki TAKEUCHIYuki YAMANASHIShigeyuki MIYAJIMAFumihiro CHINATaiki YAMAEKoki YAMAZAKIYuta SOMEINaonori SEGAYoshinao MIZUGAKIHiroaki MYORENHirotaka TERAIMutsuo HIDAKANobuyuki YOSHIKAWAAkira FUJIMAKI
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2021 Volume E104.C Issue 9 Pages 435-445

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Abstract

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

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© 2021 The Institute of Electronics, Information and Communication Engineers
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