A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

Sangyeop LEE; Kyoya TAKANO; Shuhei AMAKAWA; Takeshi YOSHIDA; Minoru FUJISHIMA

doi:10.1587/transele.2022CTS0001

Special Section on Analog Circuits and Their Application Technologies

A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

Sangyeop LEE, Kyoya TAKANO, Shuhei AMAKAWA, Takeshi YOSHIDA, Minoru FUJISHIMA

Author information

Keywords: sub-sampling PLL, low-supply-voltage, power-scalable, millimeter-wave, CMOS deeply depleted channel (DDC)

JOURNAL FREE ACCESS

2023 Volume E106.C Issue 10 Pages 533-537

DOI https://doi.org/10.1587/transele.2022CTS0001

Browse “Advance online publication” version

Details

Abstract

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

Corresponding author

Register with J-STAGE for free!