A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

Sangyeop LEE; Kyoya TAKANO; Shuhei AMAKAWA; Takeshi YOSHIDA; Minoru FUJISHIMA

doi:10.1587/transele.2022CTS0001

This article has now been updated. Please use the final version.

A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

Sangyeop LEE, Kyoya TAKANO, Shuhei AMAKAWA, Takeshi YOSHIDA, Minoru FUJISHIMA

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Keywords: Sub-sampling PLL, low-supply-voltage, power-scalable, millimeter-wave, CMOS deeply depleted channel (DDC)

JOURNAL RESTRICTED ACCESS Advance online publication

Article ID: 2022CTS0001

DOI https://doi.org/10.1587/transele.2022CTS0001

The final version of this article is now available: Vol. E106.C (2023), No. 10 pp. 533-537

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Abstract

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

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