抄録
This letter presents a 0.5V low-voltage op-amp in a standard 0.18μm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62dB, and a high unity gain bandwidth of 56MHz. The power consumption is only 350μW.
