抄録
In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of the minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased from 90mV to 343mV when the number of RO stages increased from 11 to 1Mega, which indicates the difficulty of VDD scaling in large-scale subthreshold logic circuits. The dependence of VDDmin on the number of stages is calculated using the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random VTH variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias control.
