The minimum operating voltage, V_min, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate V_min. It shows that V_min is very sensitive to the lowest necessary threshold voltage, V_t0, of MOSFETs and to threshold-voltage variations, ΔV_t, which become more significant with device scaling. There is thus a need for low-V_t0 circuits and ΔV_t-immune MOSFETs to reduce V_min. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest V_min. Various techniques are thus proposed to reduce the V_min: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce V_min of other circuit blocks, dual-V_t0 and dual-V_DD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-V_t0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for V_t-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce V_min to less than 0.5V, if combined with the low-V_t0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

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We have proposed a human-area networking technology that uses the surface of the human body as a data transmission path and uses an AC electric field signal below the resonant frequency of the human body. This technology aims to achieve a “touch and connect” intuitive form of communication by using the electric field signal that propagates along the surface of the human body, while suppressing both the electric field radiating from the human body and mutual interference. To suppress the radiation field, the frequency of the AC signal that excites the transmitter electrode must be lowered, and the sensitivity of the receiver must be raised while reducing transmission power to its minimally required level. We describe how we are developing AC electric field communication technologies to promote the further evolution of a human-area network in support of ubiquitous services, focusing on three main characteristics, enabling-transceiver technique, application-scenario modeling, and communications quality evaluation. Special attention is paid to the relationship between electro-magnetic compatibility evaluation and regulations for extremely low-power radio stations based on Japan's Radio Law.

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One Super Hi-Vision (SHV) 4k×4k@60fps fractional motion estimation (FME) engine is proposed in our paper. Firstly, two complexity reduction schemes are proposed in the algorithm level. By analyzing the integer motion cost of sub blocks in each inter mode, the mode reduction based mode pre-filtering scheme can achieve 48% clock cycle saving compared with previous algorithm. By further check the motion cost of search points around best integer candidate, the motion cost oriented directional one-pass scheme can provide 50% clock cycle saving and 36% reduction in the number of processing units (PU). Secondly, in the hardware level, two parallel improved schemes namely 16-Pel processing and MB-parallel scheme are given out in our paper, which reduces design effort to only 145MHz for SHV FME processing. Also, quarter sub-sampling is adopted in our design and 75% hardware cost is reduced for each PU. Thirdly, one unified pixel block loading scheme is proposed. About 28.67% to 86.39% pixels are reused and the related memory access is saved. Furthermore, we also give out one parity pixel organization scheme to solve memory access conflict of MB-parallel scheme. By using TSMC 0.18µm technology in worst work conditions (1.62V, 125°C), our FME engine can achieve real-time processing for SHV 4k×4k@60fps with 412k gates hardware.

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Motion compensation is widely used in many video coding standards. Due to its bandwidth requirement and complexity, motion compensation is one of the most challenging parts in the design of high definition video decoder. In this paper, we propose a high performance and low bandwidth motion compensation design, which supports H.264/AVC, MPEG-1/2 and Chinese AVS standards. We introduce a 2-Dimensional cache that can greatly reduce the external bandwidth requirement. Similarities among the 3 standards are also explored to reduce hardware cost. We also propose a block-pipelining strategy to conceal the long latency of external memory access. Experimental results show that our motion compensation design can reduce the bandwidth by 74% in average and it can real-time decode 1920x1088@30fps video stream at 80MHz.

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This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 3 × 3mm² in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0µW under a network environment.

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Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18µm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm² and the frequency of 292 MHz.

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To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64 × 64 FSSA using FSSA_DI algorithm is implemented by four Xilinx Vertex-4 FPGAs. Measurement results show that the data rates of our solution can be up to 800Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.

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A 7bit 1.0Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90nm CMOS process technology the ADC consumes 230mW with 1.2V and 2.5V supplies and has a SNR of 38dB.

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Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65nm CMOS process. The ADC has an input capacitance of 180fF and occupies an active area of 0.03mm². Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

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This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.

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A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13µm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146µW at 304MHz.

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Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The first topic is the spiral inductor design which determines the performance of the boost converter, and the second is the effect of TSV's on the boost converter. These techniques are very important in achieving a 3D-SSD with a boost converter. In the design of the inductor, the on-board inductor from 250nH to 320nH is the best design feature that meets all requirements, including high output voltage above 20V, fast rise time, low energy consumption, and area smaller than 25mm². The use of a boost converter with the proposed inductor leads to a reduction of the energy consumption during the write operation of the proposed 1.8-V 3D-SSD by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump. The feasibility of 3D-SSD's with Through Silicon Vias (TSV's) connections is also discussed. In order to maintain the advantages of the boost converter over the charge pump, the reduction of the parasitic resistance of TSV's is very important.

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A time-slicing ring oscillator (TSRO) which captures time-dependent delay degradation due to periodic transient voltage drop on a power supply network is proposed. An impact of the supply voltage fluctuations, including voltage drop and overshoot, on logic circuit delay is evaluated as a change of oscillation frequency. The TSRO is designed using standard logic cells so that it can be placed almost anywhere in a digital circuit wherein supply voltage fluctuation is concerned. We also propose a new procedure for reconstructing supply voltage waveform. The procedure enables us to accurately monitor time-dependent, effective supply voltages. The −1dB bandwidth of the TSRO is simulated to be 15.7GHz, and measured time resolution is 131ps. Measurement results of a test chip using 90-nm standard CMOS process successfully proved the feasibility of both delay degradation and effective supply voltage fluctuation measurements. Measurement of spatial voltage drop fluctuation is achieved.

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In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (V_DD) for logic circuits, the dependence of the minimum operating voltage (V_DDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90nm CMOS ring oscillators (RO's). The measured average V_DDmin of inverter RO's increased from 90mV to 343mV when the number of RO stages increased from 11 to 1Mega, which indicates the difficulty of V_DD scaling in large-scale subthreshold logic circuits. The dependence of V_DDmin on the number of stages is calculated using the subthreshold current model with random threshold voltage (V_TH) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random V_TH variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias control.

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According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a “BISER” (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.

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A physics-based equivalent circuit model of the ceramic capacitor is proposed, which can reproduce frequency characteristics of its impedance including the often observed yet hitherto physically unexplained kinks appearing above the primary series resonance frequency. The model can also account for parasitic effects of external inductances. In order to efficiently analyze and gain engineering insight into ceramic capacitors with a large number of metallic laminae, a two-dimensional method of moments is developed that treats the laminar structure as a uniform, effective medium. It turns out that the primary resonance and the kinks can be well understood and modeled by a lossy transmission line stub with a drastic wavelength reduction. The capacitor model is completed by adding components describing the skin effect and external inductances. The modeled impedance stays within a 4% margin of error up to 5GHz. The proposed model could greatly improve the accuracy of power distribution network simulation.

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Memristor is drawing more and more attraction nowadays after HP Laboratory announced its invention. Since then many researchers are taking efforts to find its applications in various areas of the information technology. Among the important applications, one of the interesting issues is the research on memristor circuits. To put forward such research, there is an urgent demand to establish a memristor SPICE model, such that people could conduct SPICE simulation to obtain the performance of the memristor circuits under their investigation. This paper reports our efforts to meet the urgent demand. Based on the memristor device fabrication technology parameters, as well as the theoretical description on memristor, we first propose memristor SPICE models, then verify the effectiveness of the proposed models by applying it to some memristor circuits. Simulation results are satisfactory.

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A methodology to automatically convert fixed point data type representations into integer data types for high level synthesis is presented in this work. Our method converts all major C operations using fixed point data types into integer data types, models quantization and overflow modes, type conversion and casting. The conversion rule for each operation is described in detail as well as a regression test environment with 600 test cases to validate the method and to verify the correctness of each conversion compared to the same cases written in SystemC. The test environment converts each test case with fixed point data types into integer data types and synthesizes them with a high level synthesis tool to generate RTL. An RTL simulation is ran and the results in turn compared to the SystemC's OSCI simulation. For all of the 600 test cases the RTL simulation results matched the SystemC results proving that each conversion is accurately modeled. A larger real test case is also presented to validate the conversion method in a complex case.

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With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from [18], [19], and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in [19]. The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.

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This paper presents generating stable and sparse reluctance/inductance matrix from the inductance matrix which is extracted under insufficient discretization. To generate the sparse reluctance matrix with guaranteed stability, the original matrix has to be (strictly) diagonally dominant M matrix. Hence, the repeated inductance extractions with a smaller grid size are necessary in order to obtain the well-defined matrix. Alternatively, this paper provides some ideas for generating the sparse reluctance matrix, even if the extracted reluctance matrix is not diagonally dominant M matrix. These ease the extraction tasks greatly. Furthermore, the sparse inductance matrix is also generated by using double inverse methods. Since reluctance components are not still supported in SPICE-like simulators, generating the sparse inductance matrix is more useful than the sparse reluctance one.

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This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0°C, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

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In this paper, a 10-Gb/s CMOS optical receiver analog front-end is designed and implemented in 0.13-µm CMOS technology. An optical receiver analog front-end includes a pre-amplifier and a post amplifier. To ensure 10-Gb/s operation, the effect of inherent photodiode parasitic capacitance should be suppressed. Thus, an advanced common-gate stage is exploited as the input stage of pre amplifier. To enhance the bandwidth without a passive inductor, a new post amplifier with active feedback and negative capacitance compensation techniques is proposed. A prototype chip has 98-dBΩ of trans-impedance gain (Z_T), corresponding 40-dB input dynamic range (5-µA to 500-µA) and minimum allowable input current (5-µA). Also, the receiver achieves the bandwidth of 7.5-GHz for 0.25-pF photodiode parasitic capacitance, and the measured optical sensitivity equals −18-dBm for 10 ^-12bit error rate (BER).

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Dynamic Voltage Scaling (DVS) is a well-known low-power design technique, which adjusts the clock speed and supply voltage dynamically to reduce the energy consumption of real-time systems. Previous studies considered the probabilistic distribution of tasks' workloads to assist DVS in task scheduling. These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy. This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption. This algorithm takes full advantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF). Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds. The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees.

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Fast Fourier Transform (FFT) is an important algorithm in many digital signal processing applications, and it often requires parallel implementation for high throughput. In this paper, we first present the SmartCell coarse-grained reconfigurable architecture targeted for stream processing. A SmartCell prototype integrates 64 processing elements, configurable interconnections, and dedicated instruction and data memories into a single chip, which is able to provide high performance parallel processing while maintaining post-fabrication flexibility. Subsequently, we present a parallel FFT architecture targeted for multi-core platforms computing systems. This algorithm provides an optimized data flow pattern that reduces both communication and configuration overheads. The proposed parallel FFT algorithm is then mapped onto the SmartCell prototype device. Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and MorphoSys implementations, respectively. SmartCell also achieves the energy efficiency gains of 2.1 and 28.9 when compared with FPGA and DSP implementations.

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In this letter, a novel 4-way X-band spatial power divider/combiner has been developed using a modified quasi-Yagi antenna transition. The divider has an insertion loss of less than 0.5dB and a power balance of +/-0.8dB over a bandwidth of 3.5GHz in the X-band. A power combiner amplifier using this circuit and four MMIC amplifiers has been demonstrated with 84% combining efficiency. The obtained results show that the modified quasi-Yagi antenna is a suitable element to develop a broadband spatial power combiner.

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This letter presents the design and analysis of phase noise optimization of a 4-GHz differential Colpitts voltage-controlled-oscillator (VCO). A low phase noise is achieved by a Colpitts oscillator and a VCO bias optimization using an amplitude control method. The measured phase noise is −134.8dBc/Hz at 1.25MHz offset frequency from 4GHz operating frequency. The VCO is implemented using 0.24µm SiGe BiCMOS process with integrated copper inductors. The wide VCO frequency range covers both PCS and IMT bands and draws about 15.9mA from a 2.7V power supply.

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A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with V_cc, so that the V_pass window margin is improved by up to 59% in 40nm MLC NAND flash memory with 2.7V V_cc. In the case of 1.8V V_cc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7V V_cc.

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