IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Analog Circuits and Related SoC Integration Technologies
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
Masaaki SODAYoji BANDOSatoshi TAKAYAToru OHKAWAToshiharu TAKARAMOTOToshio YAMADAShigetaka KUMASHIROTohru MOGAMIMakoto NAGATA
著者情報
キーワード: noise, sine wave, harmonic
ジャーナル 認証あり

2011 年 E94.C 巻 6 号 p. 1024-1031

詳細
抄録
A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5- degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20MHz to 220MHz with 1MHz steps. The SFDR of 40dB is obtained at the noise frequency of 100MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.
著者関連情報
© 2011 The Institute of Electronics, Information and Communication Engineers
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