Design for Testability That Reduces Linearity Testing Time of SAR ADCs

Tomohiko OGAWA; Haruo KOBAYASHI; Satoshi UEMORI; Yohei TAN; Satoshi ITO; Nobukazu TAKAI; Takahiro J. YAMAGUCHI; Kiichi NIITSU

doi:10.1587/transele.E94.C.1061

Special Section on Analog Circuits and Related SoC Integration Technologies

Design for Testability That Reduces Linearity Testing Time of SAR ADCs

Tomohiko OGAWA, Haruo KOBAYASHI, Satoshi UEMORI, Yohei TAN, Satoshi ITO, Nobukazu TAKAI, Takahiro J. YAMAGUCHI, Kiichi NIITSU

Author information

Tomohiko OGAWA
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Haruo KOBAYASHI
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Satoshi UEMORI
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Yohei TAN
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Satoshi ITO
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Nobukazu TAKAI
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Takahiro J. YAMAGUCHI
Department of Electronic Engineering, Graduate School of Engineering, Gunma University
Kiichi NIITSU
Department of Electronic Engineering, Graduate School of Engineering, Gunma University

Keywords: SAR ADC, testing, DC linearity, design for testability, built-in self-test

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2011 Volume E94.C Issue 6 Pages 1061-1064

DOI https://doi.org/10.1587/transele.E94.C.1061

Details

Abstract

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

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