Design of 65nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier

抄録

In this paper we present a 0.25-1.0V, 0.1-200MHz, 256×32, 65nm SRAM macro. The main design techniques include a bitline leakage prediction scheme and a non-trimmed non-strobed sense amplifier to deal with process and runtime variations and data dependence.