IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Yoshitaka HIRAMATSUHasitha Muthumala WAIDYASOORIYAMasanori HARIYAMAToru NOJIRIKunio UCHIYAMAMichitaka KAMEYAMA
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2012 年 E95.C 巻 12 号 p. 1872-1882

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抄録
The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16×16 pixel blocks.
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© 2012 The Institute of Electronics, Information and Communication Engineers
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