Improvement of Address Discharge Delay Time Using Modified Reset Waveform in AC Plasma Display Panel

抄録

In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (V_a-bias) during the ramp-up period. It is revealed that the proper V_a-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the V_a-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40ns and the address period of each subfield can be significantly reduced by about 43µs.