IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Analog Circuits and Related SoC Integration Technologies
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells
Masao TAKAYAMAShiro DOSHONoriaki TAKEDAMasaya MIYAHARAAkira MATSUZAWA
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2013 Volume E96.C Issue 6 Pages 813-819

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Abstract

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv.

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© 2013 The Institute of Electronics, Information and Communication Engineers
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