VLSI Design and Implementation of ARS for Periods Estimation

抄録

This paper proposes two VLSI implementation approaches for periods estimation hardware of periodic signals. Digital signal processing is one of the important technologies, and to estimate periods of signals are widely used in many areas such as IoT, predictive maintenance, anomaly detection, health monitoring, and so on. This paper focuses on accumulation for real-time serial-to-parallel converter (ARS) which is a simple parameter estimation method for periodic signals. ARS is simple algorithm to estimate periods of periodic signals without complex instructions such as multiplier and division. However, this algorithm is implemented only on software, suitable hardware implementation methods are not clear. Therefore, this paper proposes two VLSI implementation methods called ARS-DFF and ARS-MEM. ARS-DFF is simple and fast implementation method, but hardware scale is large. ARS-MEM reduces hardware scale by introducing an SRAM macro cell. This paper also designs both approaches using System Verilog and evaluates VLSI implementation. According to our evaluation results, both proposed methods can reduce the power consumption to less than 1/1000 compared to the implementation on a microprocessor.