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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Vol. E100.A (2017) No. 7 pp. 1464-1472

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http://doi.org/10.1587/transfun.E100.A.1464

Special Section on Design Methodologies for System on a Chip

Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.

Copyright © 2017 The Institute of Electronics, Information and Communication Engineers

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